The present invention relates to fabrication methods for integrated semiconductor circuits. More particularly, the present invention relates to fabrication methods for shallow trench isolation structures.
In the fabrication of densely packaged integrated circuits, fabricating shallow trench isolation (STI) structures around active devices is a very effective way for preventing carriers from penetrating through the substrate to neighboring devices. A common procedure for the formation of STI structures is shown in FIG. 1. In FIG. 1A, a layer of pad oxide 12 and a layer of silicon nitride 14 are sequentially formed on top of a semiconductor substrate 10. In FIG. 1B, a shallow trench 16 is formed by photolithographic masking and anisotropic etching of the covering layers 12 and 14 and the semiconductor substrate 10. In FIG. 1C, a thin liner oxide 18 is formed on the exposed silicon substrate by thermal oxidation. An oxide deposition step that follows fills up the trench 16 with an oxide material, and a chemical mechanical polishing (CMP) step that follows makes possible the structure shown in FIG. 1D. FIG. 1E shows the structure left behind once the silicon nitride layer 14 is removed. A subsequent oxide etch results in the isolation structure shown in FIG. 1F.
Once the isolation structure is completed, semiconductor devices such as EEPROM cells can be built. FIG. 2 shows a partially formed EEPROM cell. A first step in building the EEPROM cell is to form a thin gate oxide layer 32 on a silicon substrate 30. A subsequent CVD deposition of a polysilicon layer 34 forms a floating gate for the EEPROM 48. An oxynitride (ONO) layer 36 and a second polysilicon layer 38, which functions as a control gate, is subsequently formed. As it is well known to those skilled in the art, an EEPROM cell can be programmed or erased more efficiently if its coupling ratio is higher. Coupling ratio is the ratio of a first capacitance (not shown) formed between the control gate 38 and the floating gate 48 and a second capacitance (not shown) formed between the floating gate 48 and the silicon substrate 30. Since the first and second capacitances are connected in series, a higher coupling ratio means that, with all other factors remaining the same, there is a higher voltage drop between floating gate 48 and the substrate 30, making it easier and faster for electrons to tunnel through the gate oxide 32. As a result, programming and erasure of the EEPROM is quicker.
A variety of ways have been developed over the years to improve the coupling ratio of an EEPROM cell. Two obvious approaches to improve the coupling ratio are either by increasing the first capacitance (between the control gate 38 and the floating gate 48) or by decreasing the second capacitance (between the floating gate 48 and the substrate 30). It is equally well understood that the capacitance can be manipulated either through the manipulation of the capacitative surface area or the manipulation of the distance between the capacitative surfaces. One method for increasing the coupling ratio calls for the thickening of the gate oxide layer 32 while simultaneously creating a smaller tunneling region in part of the gate oxide layer to facilitate carrier transfer. Another method calls for the reduction in the area occupied by the gate oxide 32. Yet another method calls for the thinning of the oxynitride layer 36. It would also be desirable to further increase the first capacitance (between the control gate 38 and the floating gate 48) by increasing the surface area 46 occupied the oxynitride layer 36. However, with the existing method of forming the isolation trench structure, as described above and illustrated in FIG. 1, it is impossible to expand the oxynitride area 46 without expanding the gate oxide area 44 at the same time, thereby canceling any advantage of such operation in improving the coupling ratio.
Consequently, it would be desirable to have an isolation trench fabrication scheme that allows for the independent manipulation of the area occupied by the gate oxide layer 32 and the area occupied by the oxynitride layer 36.
Another limitation of the present fabrication method is that the thickness of the gate conductor is constrained by the thickness of the pad oxide layer (12 in FIG. 1). This is because the height of the gate conductor is typically limited by the height of the protruding isolation structure (40 in FIG. 2) and the height of the protruding isolation structure 40 is, in turn, determined by the total height of the silicon nitride layer (14 in FIG. 1) and the pad oxide layer 12. However, since the expansion coefficient of the silicon nitride layer 14 and that of the pad oxide layer 12 are very different, high stress could build up around the interface of the two layers 12 and 14 during subsequent manufacturing steps. Such stress can cause crystal lattice dislocation in the active area of the substrate, leading to current leakage and device failure. As a rule of thumb, in order to prevent excessive stress from building up, the thickness of the nitride layer 14 should be no more than ten times that of the pad oxide layer 12. And since it is generally desirable to have a very thin pad oxide layer 12 so that the final oxide etch could be done quickly and in a controlled manner, the thickness of the nitride layer 14 is limited as well. It would be desirable to have a fabrication method that allows the formation of a taller isolation structure without raising the thickness of the pad oxide layer 12. Yet another issue confronting IC chip manufacturer is the exposure of the sharp substrate corners (22 in FIG. 1F and 42 in FIG. 2) in the active area once the pad oxide layer 12 is etched off. Since stress tend to concentrate at sharp corner of the shallow trench, the exposed sharp corners 42 could cause junction leakage in the finished devices, contributing to device failure. It would be desirable to have a fabrication method for an isolation structure that reduces sharp corner formation and subsequent exposure.
To overcome the limitations imposed by the aforementioned fabrication process, the present invention provides a unique four-layer approach for the formation of an isolation trench structure. In a preferred embodiment of the present invention, the isolation trench fabrication process begins with the forming of a multi-layer structure on a silicon substrate, which includes the steps of forming a layer of thin pad oxide, a layer of silicon nitride, a thicker layer of silicon oxide and an even thicker layer of silicon nitride sequentially. Photolithographic masking and anisotropic etching procedures follow to form trenches in the silicon substrate. A silicon oxide material is then deposited to fill up the trenches. The top silicon nitride layer is then etched off, exposing the oxide layer and part of the trench filling oxide that appeared as a protruding structure. Using the remaining nitride layer as a natural etch stop, the exposed oxide is then etched away isotropically. With the nitride layer acting as a natural etch barrier, the etch time can be extended to create a desirable profile on the protruding oxide structure, increasing the coupling ratio through the increase in oxynitride surface area. Once a desirable profile has been achieved on the oxide structure, a nitride etch is performed to eliminate the silicon nitride layer. A short oxide etch is then performed to etch off the remaining thin pad oxide, leaving behind a protruding isolation structure that has a peak area that could be substantially smaller than foot area, thereby enable the making of EEPROM with improved coupling ratio. Furthermore, the constraint on the thickness of the protruding isolation structure is lifted by using the multiple layer structure because the thickness of the top nitride layer is no longer constrained by the need for a thin pad oxide layer.